Non-contact method for monitoring and controlling plasma charging damage in a semiconductor device

ABSTRACT

The present invention provides a method for controlling a process parameter for fabricating a semiconductor wafer. In one embodiment, the method includes forming a test substrate using a given process parameter, determining a flatband voltage of the test substrate, and modifying the given process parameter to cause the flatband voltage to approach zero. The process parameter that is modified to cause the flatband voltage to approach zero may vary. The flatband may be determined by a non-contact method, which uses a kelvin probe to measure the flatband voltage and a corona source to deposit a charge on the test substrate.

This application is a continuation of application Ser. No. 09/178,317filed Oct. 23, 1998.

TECHNICAL FIELD OF THE INVENTION

The present invention is directed in general to a process forfabricating a semiconductor device, and more specifically to a processfor measuring and controlling plasma charging damage in semiconductordevices.

BACKGROUND OF THE INVENTION

Plasma processing has become an integral part of the fabrication ofintegrated circuits since it offers advantages in terms ofdirectionality, low temperature and process convenience. However, plasmaprocessing also offers increased damage potential because of surfacecharging of floating gates in MOS devices. With the continued increasein gate oxide thickness to improve device performance, this type ofdamage is becoming more of a concern. The damage can degrade all of theelectrical properties of a gate oxide, which include the fixed oxidecharge density, the interface state density, the flatband voltage, theleakage current and the various breakdown related parameters.

Evidence is mounting that the primary cause of oxide damage duringplasma etching is charge buildup on the conductors. Plasma nonuniformityacross the wafer surface plays a major role in this damage. For example,plasma nonuniformity produces electron and ion currents that do notbalance locally and can generate oxide damage. These plasmainconsistencies are caused by hardware (e.g., poor electrode design,nonuniform and/or time-varying magnetic fields) or by a poor choice ofprocess conditions (e.g., use of highly electronegative gas, choosingflows and pressures that lead to unstable plasmas). Additional causesinclude transient surge currents produced by gas chemistry changes atendpoint and changes in plasma exciting power or coupling capacitordischarges. Etch rate uniformity does not necessarily correlate withplasma uniformity or oxide damage. For instance, a pure Cl₂ plasmacaused less damage than a plasma containing a mixture of Cl₂ and SF₆even though the pure Cl₂ plasma produced about twice the etch ratenonuniformity as the plasma with a Cl₂/SF₆ mixture.

There are three main current components at the surface of a wafer placedin an RF plasma. While at 13.56 MHZ, the largest is the RF displacementcurrent; this is usually of secondary importance in surface chargingbecause of the low impedance presented by the oxide. Next, there ispositive ion flux that is responsible for anisotropic etching. The fluxaverage is nearly constant with time and depends linearly on the localplasma density. The final component, electron flux, flows briefly inevery RF cycle to balance the ions lost from the central plasma region.In a uniform plasma, the ion and electron conduction currents locallybalance each other over the RF conduction cycle. Charging is not aproblem and the surface potential stays close to that of the substrate.

The situation for a nonuniform plasma differs significantly. Ion andelectron currents do not have to balance locally through the RF cycle,although there is a net balance over the electrode as a whole. Forexample, the electron current can be higher than ion current where theplasma potential is at a minimum; where the potential is a maximum, theopposite is true. Also, where excess ion current occurs, the imbalance(e.g., net current flux to the wafer) causes wafer surface charging andresults in increased voltage across the gate and decreased voltageacross the sheath. The charge buildup continues until the currentsbalance or the oxide begins to conduct. This feedback mechanism iscaused by the exponential dependence of electron current on sheathvoltage.

The VLSI industry is focusing on solutions to process-induced plasmadamage in product devices. Such damage is caused by cumulative netcharge deposition on wafers during plasma processing, where unbalancedplasma charges up the gate dielectric to a level exceeding thedielectric breakdown field. Because of the charge collected by the longconductive gate polysilicon chain in VLSI devices, a seemingly lowplasma charging can become multiplied by a ratio factor when dischargingthrough the gate insulator. The ratio factor, called the antenna ratio,is the gate poly area to gate dielectric area.

For the 0.25-0.35 micrometer feature devices, the circuit poly antennaratio can range from 5:1 to 50:1. The implication is that with afloating gate poly, the case of most in-process product devices prior tofirst metal, the device gate oxide can experience electrical breakdownduring plasma charging more easily than one without, by five to 50times. Because there is no breakdown current limiter, such dielectriczapping is destructive, leading to device poly to substrate leakage, anddevice yield is degraded. In the case where the plasma charging buildupmay not yet reach the breakdown but goes beyond half the breakdown, thetunneling current is sufficient to damage the oxide-silicon electronicstructure that introduces excessive interface states if not properlyannealed. Devices with interface damage drift with time. Thus the devicereliability is at stake.

Plasma-induced charging damage characterization using test structuresrequires fast-turn-around between a questionably plasma step andelectrical testing to be most useful. MOS capacitor structures providecheaper and faster fabrication than transistors and also can bepretested to insure their calibration. The C-V measurement is regardedas one of the most sensitive techniques for plasma damage in many cases.However, C-V measurements are slow, sensitive to noise and difficult toautomate. Charge-to breakdown Qbd is another option, but it requireslong times to breakdown at low gate currents. Accelerated Qbdmeasurements use larger injecting currents but lowers this measurementsensitivity. Recently, a new voltage time (V-t) method was proposedwhich uses low constant current stressing and measures the biasedvoltage change with time (dV/dt). It was found that dV/dt is related tothe initial electron trapping rate (IETR), which is proportional topre-existing damage. So far, there has been no comparison of thesensitivity of the different methods or their limitations. So, it isnecessary to establish basic understanding of these issues for futureindustry standards of damage testing. To determine whether the devicehas been damaged by fabrication charge build-up, manufacturers haveincorporated antenna structures into the semiconductor devices. Thesestructures may be employed to test the device and determine whethercharge damage has occurred in the device during the fabrication process.

Unfortunately, however, the antenna structure suffers from certaindisadvantages. For example, the antenna structure size is typicallydirectly proportional to its damage sensitivity. Therefore, to obtain areading on a very small charge, a larger antenna ratio (poly/oxideareas) structure is required. In many cases, these larger antennastructures are necessary because the charge damage that often occurs inthe device is very small.

Moreover, these antenna structures are unable to isolate the specificdevice layers that are damaged, when multi-layer chips are involved.Thus, it is not possible to determine what part of the process hascaused the charge damage, and due to the complexity of fabrication ofthe antenna structure, time delays and corresponding overall costsinvolved, frequent testing during the fabrication process is typicallyprohibitive.

Accordingly, what is needed in the art is a cost effective way todetermine process-induced damage and direct the adjustment of theappropriate process parameters on a frequent basis.

SUMMARY OF THE INVENTION

To address the above-discussed deficiencies of the prior art, thepresent invention provides a method for controlling a process parameterfor fabricating a semiconductor wafer. In one embodiment, the methodincludes forming a test substrate using a given process parameter,determining a flatband voltage of the test substrate, and modifying thegiven process parameter to cause the flatband voltage to approach zero.The process parameter that is modified to cause the flatband voltage toapproach zero may vary. For example, a deposition pressure used todeposit a dielectric layer, may be modified. Alternatively, themodification may include forming a cap layer on an oxide deposited onthe test substrate prior to forming a dielectric layer on the testsubstrate. Preferably, the flatband is determined by a non-contactmethod, which uses a kelvin probe to measure the flatband voltage and acorona source to deposit charge on the test substrate.

Thus, one aspect of the present invention provides a non-contact methodfor easily determining whether a certain fabrication process, such as adielectric deposition, produces a wafer with charge damage early in thesemiconductor devices formation. Additionally, the present inventionalso provides a method that can readily detect low levels of chargedamage that have been previously undetectable. Due to the sensitivityand accuracy of this method and the ease with which it can be conducted,substantial fabrication downtime, which is prevalent in presentprocesses, can be saved, thereby lowering the fabrication costs of thesemiconductor device.

In other embodiments, forming, determining and modifying are repeateduntil the flatband voltage approximates or reaches zero. When theflatband voltage is about zero, charge is either not present in thesemiconductor wafer, or is extremely small such that no substantialdamage results to the device's operation.

In certain embodiments, forming a test substrate includes forming anoxide layer on a silicon substrate and depositing a dielectric layer onthe oxide layer. Yet other embodiments includes determining the flatbandvoltage with a non-contact method.

In yet another embodiment, the method may further include determining aninterface trap density of the test substrate and modifying processparameters to minimize interface trap density.

The foregoing has outlined, rather broadly, preferred and alternativefeatures of the present invention so that those who are skilled in theart may better understand the detailed description of the invention thatfollows. Additional features of the invention will be describedhereinafter that form the subject of the claims of the invention. Thosewho are skilled in the art should appreciate that they can readily usethe disclosed conception and specific embodiment as a basis fordesigning or modifying other structures for carrying out the samepurposes of the present invention. Those who are skilled in the artshould also realize that such equivalent constructions do not departfrom the spirit and scope of the invention in its broadest form.

BRIEF DESCRIPTION OF THE DRAWINGS

For a more complete understanding of the present invention, reference isnow made to the following descriptions taken in conjunction with theaccompanying drawings, in which:

FIG. 1 illustrates a semiconductor device that may be used as a testdevice in a conventional test method to determine electrical properties;

FIG. 2 illustrates a graph showing the electrical properties of thesemiconductor device using the conventional test method of FIG. 1;

FIG. 3 illustrates a non-contact test method for determining electricalproperties of a test substrate according to the principles of thepresent invention; and

FIG. 4 illustrates a flowchart showing a method of testing the integrityof a semiconductor fabrication process; and

FIG. 5 illustrates is a graph showing the test results for thenon-contact test method employed in FIG. 3 and FIG. 4.

DETAILED DESCRIPTION

Referring initially to FIG. 1, illustrated is a semiconductor device 100that may be used as a test device in a conventional test method todetermine electrical properties. The semiconductor device 100 includes atransistor device 105 having a conventional stacked antenna structure115, which includes a polysilicon antenna 116.

The antenna structure 115 maximizes the charging sensitivity of oxidesto fabrication process damage, by increasing the antenna ratio (gatepoly area/gate dielectric area) during fabrication process exposure. Theresulting collected charge 119 is proportional to the antenna ratio.Typical area ratios of the antenna structure 115 may range from 5000 to100,000 times the gate area to which it is attached, resulting inincreasing charge sensitivity.

Turning now to FIG. 2, illustrated is a graph 200 showing the electricalproperties of the semiconductor device 100 using the conventional testmethod of FIG. 1. The graph 200 includes a first electricalcharacteristic 205, a second electrical characteristic 210 and a thirdelectrical characteristic 215 resulting from the electrical testsemployed. The first, second and third electrical characteristics 205,210, 215 illustrate a gate leakage current for antenna structures havingarea ratios (AR) of 8,000, 21,000 and 89,000 times their correspondinggate areas, respectively. As discussed earlier, the determination ofprocess damage using this conventional antenna structure is impracticalduring actual fabrication since use of the method does not allow thecharge damage to be isolated for multi-layer devices and is time andcost prohibitive for use between each dielectric layer.

Turning now to FIG. 3, illustrated is a non-contact test device 300 fordetermining electrical properties of a test substrate according to theprinciples of the present invention. This embodiment includes using aconventional non-contact method that uses a corona source 305, a kelvinprobe 310, a light source 315 to form a charge on a test wafer 320,which itself includes a p-type silicon substrate 321, an oxide layer 322and a dielectric layer 323.

In a conventional manner, the non-contact method initially depositscharge on the exposed top surface of the dielectric layer 323. The lightsource 315 is then used to bombard the device with photons to generateelectron-hole pairs and flatten the energy bands. Electricalmeasurements, such as surface photovoltage (SPV) and a surface voltageVs are then acquired, using the Kelvin probe 310. From these electricalmeasurements, a flatband voltage can be determined. The flatband voltageis defined as the value of this surface voltage Vs when the SPV has avalue of zero.

Turning now to FIG. 4 with continued reference to the device structureof FIG. 3, illustrated is a flowchart 400 showing a method of testingthe integrity of a semiconductor fabrication process. The methodillustrated in the flowchart 400 allows determination of whether acertain fabrication process produces a wafer with charge damage beforeactual semiconductor device formulation begins. The method begins at405, wherein it is determined that a test semiconductor device needs tobe fabricated. Then, the test wafer is formed at 410 using a selectionof fabrication process parameters. For example, the parameter to be testmay include the deposition parameters used to deposit pre-metaldielectric. In such instances, the dielectric layer 323, using thepresent deposition parameters, is deposited on the substrate 321 of thetest wafer 300. If required, the oxide layer 322 may be thermally formedon the substrate prior to the dielectric deposition to prevent leakage.However, in certain embodiments, the oxide layer 322 may not be present.The oxide layer 322 is typically thermally grown, and the dielectriclayer 323 may be deposited using known plasma deposition processes. Thenon-contact test method 300 of FIG. 3 is then performed at 415 using thetest wafer prepared at 410.

Next, the results at 415 are analyzed with a conventional non-contactmethod at 420 to determine the value of a flatband voltage of thedielectric layer 323 as deposited using the given process parameters. Ifthe flatband voltage is not near or approximately zero, the processdeposition parameters are adjusted. A new test wafer is provided and thedielectric layer is deposited using adjusted process parameters, and themethod is repeated starting with the step 410.

This method continues, until the process parameters selected result in atest wafer that produces a flatband voltage that is near or approximateszero. This indicates that the process-induced charge build-up issufficiently low assuring predictable device performance, and the methodends in a step 430. Then, semiconductor fabrication of actual productionwafers may be initiated, with high confidence, using these processparameters. The process parameter that is modified to cause the flatbandvoltage to approach zero may vary. The process parameter may be adeposition pressure, the forming of a cap layer on an oxide or someother parameter. In addition to the determination of the flatbandvoltage, the method may also include determining an interface trapdensity of the test substrate 320 that may also be used to repeatedlymodify and then test the fabrication process in order to minimize theinterface trap density. While a pre-metal dielectric has been discussed,it should be understood that the present method may be used regardingany layer within the semiconductor device.

Turning now to FIG. 5, illustrated is a graph 500 showing the testresults for the non-contact test method 300 employed in FIG. 3 and FIG.4. The graph 500 includes a first test response curve 505, a second testresponse curve 510 and a third test response curve 515. Each of thefirst, second and third test response curves 505, 510, 515 are theresults of performing the non-contact method on a test wafer 320 thathas been fabricated using a different process or process parameter.

The surface voltage Vs where the SPV equals zero is the value offlatband voltage associated with each of the test response curves.Therefore, the fabrication process that produced the first test responsecurve 505 is seen to have a flatband voltage of approximately 5 volts.This value indicates that the process-related charge damage issignificant enough to affect the device performance and must beadjusted.

Adjustment of the fabrication process resulted in the second testresponse curve 510, which produced a flatband voltage of approximately−15 volts. This value indicates that the process-related charge damageis also significant, thereby requiring another fabrication processadjustment. The third test response curve 515, obtained after furtherfabrication process adjustments, indicates a flatband voltage ofapproximately zero. This result indicates that the fabrication processparameters used to fabricate this test wafer produced minimal chargedamage and therefore are acceptable for a production run.

In summary, the present invention provides a method that can readilydetect low levels of charge damage that have been previouslyundetectable. Due to the sensitivity, accuracy and facility of thismethod, substantial fabrication downtime, which is prevalent in presentprocesses, can be saved thereby lowering the fabrication costs of thesemiconductor device.

Although the present invention has been described in detail, those whoare skilled in the art should understand that they can make variouschanges, substitutions and alterations herein without departing from thespirit and scope of the invention in its broadest form.

What is claimed is:
 1. A method of determining charge damage to adielectric layer during a semiconductor wafer fabrication process,comprising: forming a dielectric layer on a semiconductor wafer using agiven process parameter; subjecting said dielectric layer to a chargingprocess, determining a degree of charge damage of said dielectric layeras a result of said subjecting with a non-contact method; and modifyingsaid given process parameter to cause said charge damage to be reduced.2. The method as recited in claim 1 wherein forming a dielectric layerincludes forming a gate oxide layer on a silicon substrate.
 3. Themethod as recited in claim 1 wherein determining includes determining aflatband voltage.
 4. The method as recited in claim 1 whereindetermining a degree of charge damage includes: depositing a plasmacharge on a surface of said dielectric layer; bombarding said dielectriclayer with photons to photo-flatten the bands; measuring a surfacevoltage and a surface photovoltage to obtain a flatband voltagemeasurement.
 5. The method as recited in claim 4 wherein said flatbandvoltage is about zero when a charge is not present in said semiconductorwafer.
 6. The method as recited in claim 1 wherein said modifyingincludes modifying a deposition pressure.
 7. The method as recited inclaim 1 wherein forming a dielectric layer includes forming an oxidelayer on said semiconductor wafer and said method further includesforming another dielectric layer on said oxide layer.
 8. The method asrecited in claim 1 wherein determining includes determining an interfacetrap density of said dielectric layer, and modifying includes modifyingprocess parameters to minimize said interface trap density.